Symbolic timing diagrams: a visual formalism for model verification
نویسنده
چکیده
منابع مشابه
Using a Visual Formalism for Design Verification in Industrial Environments
This paper reports experiences and results gained during the evaluation of the visual formalism STD as speciication method for formal veriication, performed in cooperation with industrial partners. The visual formalism STD (Symbolic Timing Diagrams) was developed continuously since 1993 by OFFIS as a speciication method, which satisses several needs: (1) It is based on the principles used in th...
متن کاملAn environment for compositional specification verification of complex embedded systems
Model-based development processes are a widely accepted measure to avoid errors in the development of safety-critical embedded systems. Models serve as executable specifications and abstract implementations in early phases of the development. Using Modeling, requirements can be analyzed and problems can be identified in these early phases. Application of model checking can yield the formal proo...
متن کاملTamagotchis Need Not Die { Veriication of Statemate Designs
This paper presents a toolset we built for supporting veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control applications. Designs are translated into nite state machines which are optimized and then veriied by symbolic model checking. To express requirement speciications the visual formalism of symbolic timing diagrams is used. Their semantics is given ...
متن کاملVooduu: Verification of Object-Oriented Designs Using UPPAAL
The Unified Modeling Language (UML) provides sequence diagrams to specify inter-object communication in terms of scenarios. The intra-object behavior is modelled by statechart diagrams. Our tool Vooduu performs an automated consistency check on both views, i.e., it verifies automatically whether a family of UML statecharts modelling a system satisfies a set of communication and timing constrain...
متن کاملEfficient Decompositional Model Checking for Regular Timing Diagrams
Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of signals. This graphical notation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called Regular Timing Diagrams (RTD’s). RTD’s have a precise syntax, and a formal semantics that is simple and corresponds to com...
متن کامل